The present disclosure relates generally to microelectronic packaging, three-dimensional integration (3Di), and more specifically to fabrication of stacked semiconductor chip assemblies including bonding of first and second wafer articles to one another through bonding layers provided at respective surfaces thereof.
In the fabrication of stacked semiconductor chip assemblies, it can be advantageous to bond first and second wafers to one another through bonding layers provided at the respective surfaces of each wafer to form a wafer-level stacked assembly. Through silicon vias can provide vertical interconnects between conductive features of each wafer such as landing pads, traces, conductive pads or posts or traces and conductive features such as bond pads at one or more surfaces of the wafer-level assembly. Portions of the wafer-level assembly containing laterally adjacent semiconductor chips can then be severed from one another along saw lanes or “scribe lines” between the portions so as to form a plurality of assemblies each containing a plurality of vertically stacked chips.